]> git.itanic.dy.fi Git - linux-stable/commitdiff
cxl/hdm: Add more HDM decoder debug messages at startup
authorDan Williams <dan.j.williams@intel.com>
Fri, 14 Apr 2023 18:54:16 +0000 (11:54 -0700)
committerDan Williams <dan.j.williams@intel.com>
Tue, 18 Apr 2023 17:32:47 +0000 (10:32 -0700)
A recent debug session yielded a couple debug messages that were useful
for determining the reason why the driver was or was not falling back
to CXL range register emulation, and for identifying decoder setting
enumeration problems.

Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://lore.kernel.org/r/168149845668.792294.11814353796371419167.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/core/hdm.c

index abe3877cfa637114b4a3413974b9057719acb65c..7889ff203a341cbd9779172a856f307505ff9f7f 100644 (file)
@@ -130,6 +130,14 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
         */
        for (i = 0; i < cxlhdm->decoder_count; i++) {
                ctrl = readl(hdm + CXL_HDM_DECODER0_CTRL_OFFSET(i));
+               dev_dbg(&info->port->dev,
+                       "decoder%d.%d: committed: %ld base: %#x_%.8x size: %#x_%.8x\n",
+                       info->port->id, i,
+                       FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl),
+                       readl(hdm + CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i)),
+                       readl(hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(i)),
+                       readl(hdm + CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i)),
+                       readl(hdm + CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i)));
                if (FIELD_GET(CXL_HDM_DECODER0_CTRL_COMMITTED, ctrl))
                        return false;
        }
@@ -868,6 +876,10 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
        if (rc)
                return rc;
 
+       dev_dbg(&port->dev, "decoder%d.%d: range: %#llx-%#llx iw: %d ig: %d\n",
+               port->id, cxld->id, cxld->hpa_range.start, cxld->hpa_range.end,
+               cxld->interleave_ways, cxld->interleave_granularity);
+
        if (!info) {
                lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which));
                hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which));