]> git.itanic.dy.fi Git - linux-stable/commitdiff
drm/amdgpu: fix AGP addressing when GART is not at 0
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 10 Nov 2023 14:39:18 +0000 (09:39 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 29 Nov 2023 21:49:22 +0000 (16:49 -0500)
This worked by luck if the GART aperture ended up at 0.  When
we ended up moving GART on some chips, the GART aperture ended
up offsetting the AGP address since the resource->start is
a GART offset, not an MC address.  Fix this by moving the AGP
address setup into amdgpu_bo_gpu_offset_no_check().

v2: check mem_type before checking agp
v3: check if the ttm bo has a ttm_tt allocated yet

Fixes: 67318cb84341 ("drm/amdgpu/gmc11: set gart placement GC11")
Tested-by: Mario Limonciello <mario.limonciello@amd.com>
Reported-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reported-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: christian.koenig@amd.com
Cc: mario.limonciello@amd.com
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

index 5f71414190e9ab5744d040cc906757c546a580bb..d2f273d77e59557ba5185cbfa36e243788d3d86e 100644 (file)
@@ -181,6 +181,9 @@ uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
 {
        struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 
+       if (!bo->ttm)
+               return AMDGPU_BO_INVALID_OFFSET;
+
        if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)
                return AMDGPU_BO_INVALID_OFFSET;
 
index cef920a93924b60140f40fb5020871a3e0c883eb..d79b4ca1ecfc4a0028bceb48703ea2cf3d989067 100644 (file)
@@ -1527,10 +1527,14 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
 {
        struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-       uint64_t offset;
+       uint64_t offset = AMDGPU_BO_INVALID_OFFSET;
 
-       offset = (bo->tbo.resource->start << PAGE_SHIFT) +
-                amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
+       if (bo->tbo.resource->mem_type == TTM_PL_TT)
+               offset = amdgpu_gmc_agp_addr(&bo->tbo);
+
+       if (offset == AMDGPU_BO_INVALID_OFFSET)
+               offset = (bo->tbo.resource->start << PAGE_SHIFT) +
+                       amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
 
        return amdgpu_gmc_sign_extend(offset);
 }
index 05991c5c8ddbf328dd119d20eac005396a38103f..ab4a762aed5bde0a74c4f1f076dac41761b39dfe 100644 (file)
@@ -959,10 +959,8 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
                return 0;
 
        addr = amdgpu_gmc_agp_addr(bo);
-       if (addr != AMDGPU_BO_INVALID_OFFSET) {
-               bo->resource->start = addr >> PAGE_SHIFT;
+       if (addr != AMDGPU_BO_INVALID_OFFSET)
                return 0;
-       }
 
        /* allocate GART space */
        placement.num_placement = 1;