arm64: dts: mediatek: mt8173: Drop VDEC_SYS reg from decoder

Remove the VDEC_SYS register space from the decoder, so that the node
address becomes that of VDEC_MISC, solving the long-standing conflicting
addresses between this node and the vdecsys clock-controller node:

arch/arm64/boot/dts/mediatek/mt8173.dtsi:1365.38-1369.5: Warning (unique_unit_address_if_enabled): /soc/clock-controller@16000000: duplicate unit-address (also used in node /soc/vcodec@16000000)

The driver makes use of this register space, however, so also add a
phandle to the VDEC_SYS syscon to maintain functionality.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230630151436.155586-7-nfraprado@collabora.com

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index c47d7d900f28360ed03af8995246c6a689706ad0..cac4cd0a032012be0e004eb83baa6515f0f961c0 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1368,10 +1368,9 @@ vdecsys: clock-controller@16000000 {
                        #clock-cells = <1>;
                };
 
-               vcodec_dec: vcodec@16000000 {
+               vcodec_dec: vcodec@16020000 {
                        compatible = "mediatek,mt8173-vcodec-dec";
-                       reg = <0 0x16000000 0 0x100>,   /* VDEC_SYS */
-                             <0 0x16020000 0 0x1000>,  /* VDEC_MISC */
+                       reg = <0 0x16020000 0 0x1000>,  /* VDEC_MISC */
                              <0 0x16021000 0 0x800>,   /* VDEC_LD */
                              <0 0x16021800 0 0x800>,   /* VDEC_TOP */
                              <0 0x16022000 0 0x1000>,  /* VDEC_CM */
@@ -1382,6 +1381,8 @@ vcodec_dec: vcodec@16000000 {
                              <0 0x16027000 0 0x800>,   /* VDEC_HWQ */
                              <0 0x16027800 0 0x800>,   /* VDEC_HWB */
                              <0 0x16028400 0 0x400>;   /* VDEC_HWG */
+                       reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
+                                   "hwd", "hwq", "hwb", "hwg";
                        interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
                        iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
                                 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
@@ -1392,6 +1393,7 @@ vcodec_dec: vcodec@16000000 {
                                 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
                                 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
                        mediatek,vpu = <&vpu>;
+                       mediatek,vdecsys = <&vdecsys>;
                        power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
                        clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
                                 <&topckgen CLK_TOP_UNIVPLL_D2>,