pinctrl: amd: Fix mistake in handling clearing pins at startup

commit a855724dc08b8cb0c13ab1e065a4922f1e5a7552 upstream.

commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe")
had a mistake in loop iteration 63 that it would clear offset 0xFC instead
of 0x100.  Offset 0xFC is actually `WAKE_INT_MASTER_REG`.  This was
clearing bits 13 and 15 from the register which significantly changed the
expected handling for some platforms for GPIO0.

Cc: stable@vger.kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=217315
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20230421120625.3366-3-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 52d1fe5ec3e749e3b7ce03691d21439965a0defc..83bf07d03a733653a2575fe9ca388aa0c910f05c 100644 (file)
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -883,9 +883,9 @@ static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
 
                raw_spin_lock_irqsave(&gpio_dev->lock, flags);
 
-               pin_reg = readl(gpio_dev->base + i * 4);
+               pin_reg = readl(gpio_dev->base + pin * 4);
                pin_reg &= ~mask;
-               writel(pin_reg, gpio_dev->base + i * 4);
+               writel(pin_reg, gpio_dev->base + pin * 4);
 
                raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
        }