powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDB

PCIe memory address space is 1:1 mapped with u-boot.

Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map
changes in u-boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index 22f64b62d7f64039020013ab317da0429416f9f9..e0668f87779499775df3b9390869233a002563c1 100644 (file)
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -1,7 +1,7 @@
 /*
  * P1020 RDB Device Tree Source
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -553,7 +553,7 @@ pci0: pcie@ffe09000 {
                reg = <0 0xffe09000 0 0x1000>;
                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                         0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+                         0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
                interrupts = <16 2>;
@@ -580,8 +580,8 @@ pci1: pcie@ffe0a000 {
                #address-cells = <3>;
                reg = <0 0xffe0a000 0 0x1000>;
                bus-range = <0 255>;
-               ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
-                         0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
                interrupts = <16 2>;
@@ -590,8 +590,8 @@ pcie@0 {
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <0x2000000 0x0 0xc0000000
-                                 0x2000000 0x0 0xc0000000
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
                                  0x0 0x20000000
 
                                  0x1000000 0x0 0x0

diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index da4cb0d8d215b9ba7865d9814617d0c4b53623d5..e2d48fd4416ef5a6b9237869fce4db4b3b991388 100644 (file)
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -1,7 +1,7 @@
 /*
  * P2020 RDB Device Tree Source
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -537,7 +537,7 @@ pci0: pcie@ffe09000 {
                reg = <0 0xffe09000 0 0x1000>;
                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                         0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+                         0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
                interrupts = <25 2>;
@@ -564,8 +564,8 @@ pci1: pcie@ffe0a000 {
                #address-cells = <3>;
                reg = <0 0xffe0a000 0 0x1000>;
                bus-range = <0 255>;
-               ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
-                         0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
                interrupts = <26 2>;
@@ -574,8 +574,8 @@ pcie@0 {
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <0x2000000 0x0 0xc0000000
-                                 0x2000000 0x0 0xc0000000
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
                                  0x0 0x20000000
 
                                  0x1000000 0x0 0x0

diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index 0fe93d0c8b2e853d2a33a51ab3bb8efe05dbfa97..b69c3a5dc8580706e8348d4bc4a33f8b329d9f8f 100644 (file)
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -6,7 +6,7 @@
  * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
  * eth1, eth2, sdhc, crypto, global-util, pci0.
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -342,7 +342,7 @@ pci0: pcie@ffe09000 {
                reg = <0 0xffe09000 0 0x1000>;
                bus-range = <0 255>;
                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                         0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+                         0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
                interrupts = <25 2>;

diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
index e95a51285328706c71621b0fbde402c71f2f83d2..7a31d46c01b011bdee300b3dfe713983db2fe1b9 100644 (file)
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -7,7 +7,7 @@
  *
  * Please note to add "-b 1" for core1's dts compiling.
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009-2011 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -162,8 +162,8 @@ pci1: pcie@ffe0a000 {
                #address-cells = <3>;
                reg = <0 0xffe0a000 0 0x1000>;
                bus-range = <0 255>;
-               ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
-                         0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+               ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                         0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
                clock-frequency = <33333333>;
                interrupt-parent = <&mpic>;
                interrupts = <26 2>;
@@ -172,8 +172,8 @@ pcie@0 {
                        #size-cells = <2>;
                        #address-cells = <3>;
                        device_type = "pci";
-                       ranges = <0x2000000 0x0 0xc0000000
-                                 0x2000000 0x0 0xc0000000
+                       ranges = <0x2000000 0x0 0x80000000
+                                 0x2000000 0x0 0x80000000
                                  0x0 0x20000000
 
                                  0x1000000 0x0 0x0