]> git.itanic.dy.fi Git - linux-stable/commitdiff
drm/i915/lnl: Remove watchdog timers for PSR
authorMika Kahola <mika.kahola@intel.com>
Tue, 10 Oct 2023 09:52:33 +0000 (12:52 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 1 Feb 2024 00:19:11 +0000 (16:19 -0800)
[ Upstream commit a2cd15c2411624a7a97bad60d98d7e0a1e5002a6 ]

Watchdog timers for Lunarlake HW were removed for PSR/PSR2
The patch removes the use of these timers from the driver code.

BSpec: 69895

v2: Reword commit message (Ville)
    Drop HPD mask from LNL (Ville)
    Revise masking logic (Jouni)
v3: Revise commit message (Ville)
    Revert HPD mask removal as irrelevant for this patch (Ville)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231010095233.590613-1-mika.kahola@intel.com
Stable-dep-of: f9f031dd21a7 ("drm/i915/psr: Only allow PSR in LPSP mode on HSW non-ULT")
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/i915/display/intel_psr.c

index 97d5eef10130df56bbeccb292363800e849d664f..848ac483259b2a35804fb30c8e4c43f9aa4b0cd3 100644 (file)
@@ -674,7 +674,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 
        val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
 
-       val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
+       if (DISPLAY_VER(dev_priv) < 20)
+               val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time);
+
        if (IS_HASWELL(dev_priv))
                val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 
@@ -1399,8 +1401,10 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
         */
        mask = EDP_PSR_DEBUG_MASK_MEMUP |
               EDP_PSR_DEBUG_MASK_HPD |
-              EDP_PSR_DEBUG_MASK_LPSP |
-              EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+              EDP_PSR_DEBUG_MASK_LPSP;
+
+       if (DISPLAY_VER(dev_priv) < 20)
+               mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
 
        /*
         * No separate pipe reg write mask on hsw/bdw, so have to unmask all