]> git.itanic.dy.fi Git - linux-stable/commitdiff
dt-bindings: PCI: dwc: Add max-link-speed common property
authorSerge Semin <Sergey.Semin@baikalelectronics.ru>
Sun, 13 Nov 2022 19:12:47 +0000 (22:12 +0300)
committerLorenzo Pieralisi <lpieralisi@kernel.org>
Wed, 23 Nov 2022 15:01:54 +0000 (16:01 +0100)
In accordance with [1] DW PCIe controllers support up to Gen5 link speed.
Let's add the max-link-speed property upper bound to 5 then. The DT
bindings of the particular devices are expected to setup more strict
constraint on that parameter.

[1] Synopsys DesignWare Cores PCI Express Controller Databook, Version
5.40a, March 2019, p. 27

Link: https://lore.kernel.org/r/20221113191301.5526-7-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

index 91d24e400dfcc6d91a7bb67f3dac7b0a2c7895cd..e63c21783fc1f560f95be551981bc59bdae36e92 100644 (file)
@@ -54,6 +54,9 @@ properties:
       the peripheral devices available on the PCIe bus.
     maxItems: 1
 
+  max-link-speed:
+    maximum: 5
+
   num-lanes:
     description:
       Number of PCIe link lanes to use. Can be omitted if the already brought
index dcd521aed21307fcbb920745031cea99722222be..fc3b5d4ac2450ab113f423b89b0501ba5052c866 100644 (file)
@@ -55,4 +55,6 @@ examples:
 
       phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>;
       phy-names = "pcie0", "pcie1", "pcie2", "pcie3";
+
+      max-link-speed = <3>;
     };
index d9512f7f7124a7804421f35e68586210cde55f3e..e787b972758979dc0dceeb9fb15e61257ab87086 100644 (file)
@@ -74,4 +74,5 @@ examples:
       phy-names = "pcie";
 
       num-lanes = <1>;
+      max-link-speed = <3>;
     };