Makefile: Reduce wildcard usage

Having wildcards in the Makefile is error prone in situations where
there are unrelated files in the source tree that are not related to
the actual project. For example, if some source files have been
renamed and there are leftover .*.o.d files that still contain the old
source files. Then make will incorrectly determine that some old files
would still be needed even though they are not part of the project any
more.

Signed-off-by: Timo Kokkonen <kaapeli@itanic.dy.fi>

diff --git a/Makefile b/Makefile
index 0d38ebb8f551a71683b227ec2e2efc5a4c88a4da..a27a3e34871eb7c61805b2da7a90c934807552c8 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -10,6 +10,8 @@ CHECKPATCH=/usr/src/linux/scripts/checkpatch.pl
 
 PLANET_OBJS=main.o random.o vector.o planet.o camera.o quadtree.o
 PLANET_DEBUG_OBJS= $(patsubst %.o,%-debug.o,$(PLANET_OBJS))
+ALL_OBJS = $(PLANET_OBJS) $(PLANET_DEBUG_OBJS)
+ALL_DEBS = $(patsubst %.o,.%.o.d,$(ALL_OBJS))
 
 sdl-planet: $(PLANET_OBJS)
        gcc $(LIBS) -o $@ $(PLANET_OBJS)
@@ -36,9 +38,9 @@ TAGS:
        @etags *.[ch]
 
 clean:
-       rm -rfv $(PLANET_OBJS) $(PLANET_DEBUG_OBJS) *~ sdl-planet TAGS .*.d \
+       rm -rfv $(ALL_OBJS) *~ sdl-planet TAGS $(ALL_DEBS) \
                debug-planet
 
 .PHONY: all clean TAGS
 
--include .*.d
+-include $(ALL_DEBS)