]> git.itanic.dy.fi Git - linux-stable/commitdiff
arm64: dts: renesas: r8a779g0: Correct avb[01] reg sizes
authorGeert Uytterhoeven <geert+renesas@glider.be>
Sun, 11 Feb 2024 14:21:31 +0000 (15:21 +0100)
committerSasha Levin <sashal@kernel.org>
Tue, 26 Mar 2024 22:16:49 +0000 (18:16 -0400)
[ Upstream commit 7edbb5880dc3317a5eaec2166de71ff394598e6b ]

All Ethernet AVB instances on R-Car V4H have registers related to UDP/IP
support, but the declared register blocks for the first two instances
are too small to cover them.

Fix this by extending the register block sizes.

Fixes: 848c82db56923a8b ("arm64: dts: renesas: r8a779g0: Add RAVB nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/83437778614a7c96f4d8f1be98dffeee29bb4a0b.1707660323.git.geert+renesas@glider.be
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/renesas/r8a779g0.dtsi

index 0c83940b3d8a1088ed54cb08553dd8d443aa2fa9..d7677595204dc061172d32a0106cd2e23b5ddc76 100644 (file)
@@ -767,7 +767,7 @@ channel7 {
                avb0: ethernet@e6800000 {
                        compatible = "renesas,etheravb-r8a779g0",
                                     "renesas,etheravb-rcar-gen4";
-                       reg = <0 0xe6800000 0 0x800>;
+                       reg = <0 0xe6800000 0 0x1000>;
                        interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
@@ -814,7 +814,7 @@ avb0: ethernet@e6800000 {
                avb1: ethernet@e6810000 {
                        compatible = "renesas,etheravb-r8a779g0",
                                     "renesas,etheravb-rcar-gen4";
-                       reg = <0 0xe6810000 0 0x800>;
+                       reg = <0 0xe6810000 0 0x1000>;
                        interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,