clk: renesas: r8a779g0: Fix PCIe clock name

[ Upstream commit 096311157d2a6bb8f06e28e1143e2a5de6a0183b ]

Fix a typo in the name of the module clock for the second PCIe channel.

Fixes: 5ab16198b431ca48 ("clk: renesas: r8a779g0: Add PCIe clocks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f582067564f357e2183d3db67b217084ecb51888.1706608032.git.geert+renesas@glider.be
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 5974adcef3eda1947dfd6476b32b5c70b82e9162..31b13c997a057dafd62cc49c7e5be2310b4f30cb 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -193,7 +193,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("msi4",         622,    R8A779G0_CLK_MSO),
        DEF_MOD("msi5",         623,    R8A779G0_CLK_MSO),
        DEF_MOD("pciec0",       624,    R8A779G0_CLK_S0D2_HSC),
-       DEF_MOD("pscie1",       625,    R8A779G0_CLK_S0D2_HSC),
+       DEF_MOD("pciec1",       625,    R8A779G0_CLK_S0D2_HSC),
        DEF_MOD("pwm",          628,    R8A779G0_CLK_SASYNCPERD4),
        DEF_MOD("rpc-if",       629,    R8A779G0_CLK_RPCD2),
        DEF_MOD("scif0",        702,    R8A779G0_CLK_SASYNCPERD4),