]> git.itanic.dy.fi Git - linux-stable/commitdiff
drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequence
authorJosé Roberto de Souza <jose.souza@intel.com>
Thu, 13 Jan 2022 17:48:26 +0000 (09:48 -0800)
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>
Mon, 17 Jan 2022 10:19:41 +0000 (10:19 +0000)
TC voltage swing programming sequence was updated with a new step.

BSpec: 54956
Cc: stable@vger.kernel.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220113174826.50272-1-jose.souza@intel.com
(cherry picked from commit 5ff59dddacd4738edcbd01847d9df7682348cf86)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
drivers/gpu/drm/i915/display/intel_ddi.c
drivers/gpu/drm/i915/i915_reg.h

index 9c9d574f0b8c3dd72b105f0788e8320335e1531c..cab505277595dec8dfcc2a536691c3c1cfa45559 100644 (file)
@@ -1298,6 +1298,28 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 
                intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
                             DKL_TX_DP20BITMODE, 0);
+
+               if (IS_ALDERLAKE_P(dev_priv)) {
+                       u32 val;
+
+                       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+                               if (ln == 0) {
+                                       val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
+                                       val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
+                               } else {
+                                       val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
+                                       val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
+                               }
+                       } else {
+                               val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
+                               val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
+                       }
+
+                       intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
+                                    DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
+                                    DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
+                                    val);
+               }
        }
 }
 
index 4c28dadf8d695b16e44da42745092c980bcb0371..971d601fe75123b2b65f3529ef6c4a5ee6a214dc 100644 (file)
@@ -11166,8 +11166,12 @@ enum skl_power_gate {
                                                     _DKL_PHY2_BASE) + \
                                                     _DKL_TX_DPCNTL1)
 
-#define _DKL_TX_DPCNTL2                                0x2C8
-#define  DKL_TX_DP20BITMODE                            (1 << 2)
+#define _DKL_TX_DPCNTL2                                        0x2C8
+#define  DKL_TX_DP20BITMODE                            REG_BIT(2)
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK     REG_GENMASK(4, 3)
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val)     REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val))
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK     REG_GENMASK(6, 5)
+#define  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val)     REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val))
 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
                                                     _DKL_PHY1_BASE, \
                                                     _DKL_PHY2_BASE) + \